1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a transistor in a semiconductor device, which can improve the refresh characteristics of the device.
2. Description of the Prior Art
Recently, as the design rule of a device pattern shrinks below 100 nm, the channel length of a cell transistor corresponding thereto is also very reduced. As a result, the existing planar transistor structures encounter limitations in realizing the Vt target of the cell transistor required in a specific device. For this reason, a method for forming a transistor with a recessed channel structure was proposed. This transistor with the recessed channel structure has a channel length secured by selectively etching a portion of the active region of a substrate, which corresponds to a region where a gate is to be formed.
FIG. 1 is a cross-sectional view for explaining a method for manufacturing a transistor in a semiconductor device according to the prior art. As shown in FIG. 1, the silicon substrate 10 is first provided which has active and field regions defined thereon and the device isolation film 11 in the field region. Then, a portion of the substrate 10 corresponding to a gate formation region, is recessed by selective etching to form the groove 12 (recessed channel structure). Following this, well ion implantation, channel ion implantation processes and the like are sequentially performed in a state where a screen oxide film (not shown) has been formed on the surface of the substrate 10 including the groove 12. The channel ion implantation process is performed with an ion implantation dose of about 1E13 atoms/cm2. 
Thereafter, on the surface of the substrate 10 including the groove 12, a gate oxide film (not shown), a gate conductive film (not shown) and a gate hard mask film (not shown) are sequentially formed and then selectively etched to form the gate 16 in the groove 12. In FIG. 1, the reference numeral 13 designates a gate oxide film remaining after the etching, the reference numeral 14 designates a gate conductive film remaining after the etching, and the reference numeral 15 designates a gate hard mask film remaining after the etching. Next, low-concentration impurity ions are implanted into the substrate 10 at both sides of the gate 16 so as to form lightly doped drains (LDDs). Subsequently, a spacer 18 are formed on both sidewalls of the gate 16, and then, high-concentration impurity ions are implanted into the substrate 10 at both sides of the gate 16 including the spacer 18 so as to form the source and drain regions 19.
FIG. 2 shows problems occurring in the prior art and shows the simulation results for potential distribution in the cell transistor having the recessed channel structure. The simulation results were obtained under conditions where gate voltage is referenced to ground and a bias voltage of 1.0 V is applied to a storage node. In the method for manufacturing the transistor of a semiconductor device according to the prior art, as shown in FIG. 2, depletion regions in the channel regions corresponding to the sides of the gate 16 are greatly enlarged so as to cause leakage current. Thus, the data retention time of the device is shortened, resulting in deterioration in the refresh characteristics of the device. In FIG. 2, the reference character “A” designates a region with the most severe depletion.